3.1 About AMBA AHB
* burst transfer
* slpit transaction
* single cycle bus master handover
* single clock edge operation
* non-tristate implementation
* wider data bus configurations
3.1.1 A typical AMBA AHB-based microcontroller
3-1 A typical AMBA AHB-based system
3.2 Bus interconnection
3-2 Multiplexor interconnection
central multiplexor interconnection scheme...
The arbiter determines which master has its address and control signals routed to all of the slaves.
A decoder is required to control the read data and reponse signal multiplexor, which selects the appropriate signals from slave.
3.3 Overview of AMBA AHB operation
1. A master asserts a request signal to the arbiter.
2. The arbiter indicates when the master will be granted use of the bus.
3. A granted bus master starts a transfer.
- Every transfer consists of ...
+ an address and control cycle
+ one or more cycles for the data
- The address cannot be extended, but the data can be extended using the HREADY sig.
- During a transfer the slave shows the status using the HRESP [1:0] signals.
(4. Handover after burst)
3-18. Handover after busrt
3.4 Basic transfer
3-3 Simple transfer
3-4 transfer with wait state
3-5 multiple transfers
-The transfer to address B is one wait state
-Extending the data phase of the transfer to address B has the effect of extending the address phase of the transfer to address C